1. Field of the Invention
The present invention relates to a MEMS-topped integrated circuit and, more particularly, to a MEMS-topped integrated circuit with a stress relief layer and a method of forming the circuit.
2. Description of the Related Art
A micro-electromechanical system (MEMS) inductor is a semiconductor structure that is fabricated using the same types of steps (e.g., the deposition of layers of material and the selective removal of the layers of material) that are used to fabricate conventional analog and digital CMOS circuits.
MEMS inductors can be formed as single or multiple loop coil structures. When greater inductance is required, the coil structure is typically formed around a magnetic core structure. Core structures formed from laminated Ni—Fe have been shown to have low eddy current losses, high magnetic permeability, and high saturation flux density.
MEMS inductors have been formed as stand-alone devices, and as on-chip devices where a MEMS inductor is formed on the top surface of a semiconductor chip that includes a circuit, such as a switching regulator, that is connected to the MEMS inductor. Fabricating a MEMS inductor on a semiconductor chip that includes a circuit which is connected to the inductor eliminates the electrical losses that would otherwise be associated with connecting an external stand-alone inductor to the circuit with bond wire connections.
Further, fabricating a MEMS inductor on a semiconductor chip that includes the circuit eliminates the circuit board area that would otherwise be required to accommodate an external stand-alone inductor, and also eliminates the assembly steps that would otherwise be required to place the external stand-alone inductor onto a circuit board.
FIG. 1 shows a cross-sectional view that illustrates an example of a prior-art semiconductor wafer 100 that includes analog circuits and MEMS inductors. As shown in FIG. 1, semiconductor wafer 100 includes a number of identical die-sized substrate regions 110, and a corresponding number of identical metal interconnect structures 112 that are connected to the substrate regions 110.
Each substrate region 110 includes a number of structures, such as resistors, transistors, capacitors, diodes, and similar devices, which are formed in and on the substrate region 110. Each metal interconnect structure 112, in turn, is a multi-layered structure that electrically interconnects together the various devices that are formed in a substrate region 110 to realize an electrical circuit.
As further shown in FIG. 1, the top section of each metal interconnect structure 112 includes a number of conductive structures 114, such as aluminum traces, and a layer of passivation material 116, such as silicon nitride, silicon oxide, or a combination of the two, that touches and isolates the conductive structures 114.
In addition, a number of openings are formed in the layer of passivation material 116 to expose selected regions SR1 on the top surfaces of the conductive structures 114 in each metal interconnect structure 112. The selected regions SR1, in turn, form connection points for a copper-topped structure. (Only one selected region SR1 is shown for clarity.)
Further, openings are also formed in the layer of passivation material 116 to expose selected regions SR2 and SR3 on the top surfaces of the conductive structures 114 in each metal interconnect structure 112. The selected regions SR2 and SR3 form first and second connection points for a MEMS inductor.
Semiconductor wafer 100 also includes a number of identical copper-topped structures 118 and a number of identical copper MEMS inductors 120 that are formed on the metal interconnect structures 112. Each copper-topped structure 118, which includes vias, traces, and pads, touches the passivation layer 116 and the selected regions SR1 of a metal interconnect structure 112. In operation, each copper-topped structure 118 provides signal and power routing, and external electrical connection points for an integrated circuit. Thus, once packaged, bonding wires can be connected to the pad regions of each copper-topped structure 118.
Each copper MEMS inductor 120, in turn, includes a base conductive plate 122 with a via extension 122A that touches the passivation layer 116 and the selected region SR2 of a metal interconnect structure 112, and a conductive plug 124 with a via extension 124A that touches the passivation layer 116 and the selected region SR3 of a metal interconnect structure 112.
Each MEMS inductor 120 further includes a top conductive plate 126 that lies over the base conductive plate 122. In the present example, the widths and thicknesses of the plates 122 and 126 are substantially identical. Each top conductive plate 126 has a first via extension 126A that touches a base conductive plate 122 of a metal interconnect structure 112, and a second via extension 126B that touches a conductive plug 124 of a metal interconnect structure 112. In addition, base conductive plate 122, top conductive plate 126, and the via extensions 126A and 126B, define an enclosed region 130 that lies only between the base and top conductive plates 122 and 126, and the via extensions 126A and 126B.
In the FIG. 1 example, each MEMS inductor 120 also includes a magnetic core structure 132 that is located within enclosed region 130, and within no other enclosed regions. Magnetic core structure 132, which is electrically isolated from all other conductive regions, can be implemented in a number of prior-art fashions. For example, magnetic core structure 132 can be implemented with a number of laminated permalloy (Ni—Fe) cores 134 as described in U.S. Pat. No. 7,250,842, issued on Jul. 31, 2007 to Peter Johnson, et al., which is hereby incorporated by reference. The thickness of the laminations must be thin enough to minimize eddy currents.
As further shown in FIG. 1, semiconductor wafer 100 additionally includes an isolation film 136 that touches passivation layer 116, the copper-topped structures 118, and the copper MEMS inductors 120. Isolation film 136 can be implemented with, for example, an oxide or benzocyclobutene (BCB).
In operation, a current I1 can flow into a MEMS inductor 120 through base conductive plate 122 by way of via extension 122A and selected region SR2, and flow out of conductive plug 124 via selected region SR3. A current I2 can also flow in the opposite direction, flowing into MEMS inductor 120 through conductive plug 124 by way of selected region SR3, and out along via extension 122A of base conductive plate 122 and selected region SR2. A current flowing through an inductor generates a magnetic field which produces a magnetic flux density. The magnetic flux density, in turn, is a measure of the total magnetic effect that is produced by the current flowing through the inductor.
One problem with the formation of semiconductor wafer 100 is that the thick isolation film and copper film that are used to produce MEMS inductor 120 also produce a large lateral stress. The large lateral stress, in turn, can cause semiconductor wafer 100 to bow. A large wafer bow complicates subsequent process steps and introduces electrical shifts in the underlying circuits. In addition, severe lateral stress can also cause a semiconductor wafer to crack or break, or layers of material to separate from the substrate.
The problems caused by excessive lateral stress are not limited to MEMS inductors, but can also occur during the formation of other MEMS structures, such as switches, actuators, and sensors, which are fabricated with thick films of high-stress material (e.g., 5 μm-100 μm of combined metal and dielectric layers), such as the isolation film and the copper film, that are formed on the top surface of passivation layer 116.
A large lateral stress results when one material is formed on another material that has different material properties, such as a different internal stress or a different coefficient of thermal expansion. For example, the copper and permalloy (core) structures of an inductor can develop large internal stresses that result from the processes that are used to form the structures.
With copper, depending on the conditions (including impurities), the atoms in a copper electroplating process may not have sufficient time to rearrange themselves in a minimal energy state configuration to form a relaxed no-stress film. When the atoms fail to obtain the minimal energy state, the resulting internal stresses pull to reduce the sizes of the copper structures.
However, since the copper structures are atomically bonded to an adjoining passivation layer, the adjoining passivation layer has the effect of stretching a copper structure beyond the form the copper structure would otherwise take, introducing tensile stress. However, as the thickness of the copper structure increases, the magnitude of the internal stress increases. When the magnitude of the internal stress, alone or in combination with other stresses, becomes dominant, the wafer begins to bow. Similarly, isolation film 136 also has a large internal stress that introduces tensile stress.
Materials which have different thermal expansion coefficients are materials which expand or contract at different rates over a range of temperatures. For example, silicon oxide and silicon nitride of passivation layer 116 have coefficients of thermal expansion of about 3 ppm/° C. On the other hand, a metal, such as copper, can have a thermal expansion coefficient of about 15 ppm/° C., a factor of five greater.
Thus, the internal stress that can be produced by the process used to fabricate a thick film, in combination with the thermal expansion mismatch effects, can result in the development of a large lateral stress which, in turn, can bow the semiconductor wafer or, in extreme cases, destroy the semiconductor wafer.
Most current-generation process tools, such as aligners and chemical-mechanical-polishers, can accommodate a wafer bow of approximately 200 μm. However, when an array of thick-film MEMS structures, such as an array of MEMS inductors 120, is formed on the passivation layer over an array of analog integrated circuits, the wafer bow can be much larger. For example, wafer bows of as large as 1,000 μm have been observed during the fabrication of MEMS power inductors on the top surfaces of switching regulator chips.
One approach to addressing the lateral stress problem is to include stress relief breaks such as scribe lines. For example, scribe lines can be formed in isolation film 136 around the MEMS inductors 120 to reduce the stress introduced by isolation film 136. However, features such as scribe lines provide little wafer bow relief because the thickness of isolation film 136 is relatively large.
Another approach is to form a compressive film over the wafer to offset the net tensile nature of the MEMS devices. In other words, if an array of MEMS inductors introduces a positive bow to the semiconductor wafer, in this approach a film is formed over the wafer which introduces an offsetting negative bow to the semiconductor wafer. This approach, however, can significantly increase the height of the integrated circuit because the offsetting film and the films used to form the MEMS devices are comparable in thickness.
Thus, there is a need for an approach to reducing wafer bow that occurs while forming an array of MEMS devices, such as MEMS inductors, on the top surface of the passivation layer of a wafer over a corresponding array of analog integrated circuits.